Semiconductor chips have contact terminals such as pillars, pads, solder bumps, etc. for providing external electrical access to the chip. Many chip-to-chip and chip-to-board applications have a high contact terminal count. As the number of chip contact terminals increases, the dimensions of the contact terminals should decrease. Otherwise the probability of failure increases. More than one contact terminal can be used for the same signal to address the increased risk of failure. However, if all or even some I/O (input/output) signals are designed with redundancy, chip I/O density increases significantly or the chip size must increase. For a regular orthogonal I/O arrangement, the distance i.e. pitch between adjacent individual interconnects must be reduced by √{square root over (2)} in the case of 2× redundancy, by √{square root over (3)} in the case of 3× redundancy, etc. in order not to increase chip size. If the pitch is reduced in this way, the liquefiable solder volume also must be reduced. Otherwise the risk of solder shorts between adjacent interconnects increases. However, reducing the liquefiable solder volume increases the risk of contact opens even if chip warpage is very low.
A non-orthogonal chip I/O arrangement such as a hexagonal arrangement can provide a denser I/O arrangement. However, nonuniform I/O arrangements restrict chip and/or substrate metal trace routing. Thermo-compression bonding can be used in the case of extremely small pitches so as to realize very small liquefiable solder volumes. However, thermo-compression bonding is more expensive than normal flip chip processes such as mass reflow with capillary underfill.
In view of the above, there is a need for more reliable and less costly high density semiconductor chip contact terminals.